Figure 6-10. Branch Instruction Timing - IBM PowerPC 750GX User Manual

Figure 6-10. Branch Instruction Timing

0
•••
0 add
1 add
2 bc
3 mulhw
4 bc
5 fadd
Instruction
Queue
3
2 (bc)
1
0
Completion
Queue
* Instructions 5 and 6 are not in the IQ in clock cycle 5. Here, the fetch stage shows cache latency.
1. During clock cycle 0, instructions 0 and 1 are dispatched to their respective execution units. Instruction 2
is a branch instruction that updates the CTR. It is predicted as not taken in clock cycle 0. Instruction 3 is a
Multiply High Word (mulhw) instruction on which instruction 4 depends.
gx_06.fm.(1.2)
March 27, 2006
1 2 3
T0 add
T1 add
T2 add
T3 add
T4 and
T5 or
5 T5
4 T4
3 T1 T3
2 T0 T2
3 T1
2 T0
1 1 3
0 0 2
IBM PowerPC 750GX and 750GL RISC Microprocessor
4 5 6
5 fadd *
6 and*
T5 (8)
T4 (7)
T3 6
T2 5
T1
T0
3
User's Manual
7 8 9
Fetch
In dispatch entry (IQ0/IQ1)
Predict
Execute
Complete (In CQ)
In retirement entry (CQ0/CQ1)
•••
(8) (8)
(7) (7)
6 6 6
5 5 5
Instruction Timing
Page 231 of 377
10
(8)
(7)
6
5