Table 6-9. Load-And-Store Instructions - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Table 6-9 shows load-and-store instruction latencies. Pipelined load/store instructions are shown with cycles
of total latency and throughput cycles separated by a colon.

Table 6-9. Load-and-Store Instructions

Instruction
Data Cache Block Flush
Data Cache Block
Invalidate
Data Cache Block Store
Data Cache Block
Touch
Data Cache Block
Touch for Store
Data Cache Block set to
Zero
External Control In
Word Indexed
External Control Out
Word Indexed
Instruction Cache Block
Invalidate
Load Byte and Zero
Load Byte and Zero with
Update
Load Byte and Zero with
Update Indexed
Load Byte and Zero
Indexed
Load Floating-Point
Double
Load Floating-Point
Double with Update
Load Floating-Point
Double with Update
Indexed
Load Floating-Point
Double Indexed
Load Floating-Point
Single
Load Floating-Point
Single with Update
Load Floating-Point
Single with Update
Indexed
1. For cache operations, the first number indicates the latency in finishing a single instruction; the second indicates the throughput for
back-to-back cache operations. Throughput might be larger than the initial latency, as more cycles might be needed to complete
the instruction to the cache, which stays busy keeping subsequent cache operations from executing.
2. The throughput number of six cycles for dcbz assumes it is to nonglobal (M = 0) address space. For global address space,
throughput is at least 11 cycles.
3. Load/store multiple/string instruction cycles are represented as a fixed number of cycles plus a variable number of cycles, where n
is the number of words accessed by the instruction.
Instruction Timing
Page 244 of 377
(Page 1 of 4)
Primary
Mnemonic
Opcode
dcbf 31
dcbi 31
dcbst 31
dcbt 31
dcbtst 31
dcbz 31
eciwx 31
ecowx 31
icbi 31
lbz 34
lbzu 35
lbzux 31
lbzx 31
lfd 50
lfdu 51
lfdux 31
lfdx 31
lfs 48
lfsu 49
lfsux 31
Extended
Unit
Opcode
86 LSU
470 LSU
54 LSU
278 LSU
246 LSU
1014 LSU
310 LSU
438 LSU
982 LSU
— LSU
— LSU
119 LSU
87 LSU
— LSU
— LSU
631 LSU
599 LSU
— LSU
— LSU
567 LSU
Cycles Serialization
1
3:5 Execution
1
3:3 Execution
1
3:5 Execution
2:1 —
2:1 —
12
3:6 Execution
2:1 —
2:1 —
1
3:4 Execution
2:1 —
2:1 —
2:1 —
2:1 —
2:1 —
2:1 —
2:1 —
2:1 —
2:1 —
2:1 —
2:1 —
gx_06.fm.(1.2)
March 27, 2006