Timing Examples; Figure 8-16. Mei Cache-Coherency Protocol-State Diagram (Wim = 001) - IBM PowerPC 750GX User Manual

Figure 8-16. MEI Cache-Coherency Protocol—State Diagram (WIM = 001)
RH
Bus Transactions
SH = Snoop Hit
RH = Read Hit
RM = Read Miss
WH = Write Hit
WM = Write Miss
SH/CRW = Snoop Hit, Cacheable Read/Write

8.5 Timing Examples

This section shows timing diagrams for various scenarios. Figure 8-17 on page 310 illustrates the fastest
single-beat reads possible for the 750GX. This figure shows both minimal latency and maximum single-beat
throughput. By delaying the data-bus tenure, the latency increases, but, because of split-transaction pipe-
lining, the overall throughput is not affected unless the data-bus latency causes the third address tenure to be
delayed.
Note that all bidirectional signals are tristated between bus tenures.
gx_08.fm.(1.2)
March 27, 2006
Invalid
SH/CRW
WM
WH
Modified
SH
WH
IBM PowerPC 750GX and 750GL RISC Microprocessor
SH/CRW
RM
Exclusive
SH/CIR
User's Manual
RH
Snoop Push
Cache Block Fill
Bus Interface Operation
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