Index - IBM PowerPC 750GX User Manual

Index

A
AACK (address acknowledge) signal
ABB (address bus busy) signal
Address bus
,
address tenure 284
address transfer
,
An 254
,
APE 294
address transfer attribute
,
CI 260
,
GBL 261
, ,
TBST 259 294
, ,
TSIZn 258 294
, ,
TTn 256 294
,
WT 260
address transfer start
, ,
TS 253 292
address transfer termination
,
AACK 262
,
ARTRY 263
terminating address transfer
,
arbitration signals 251
,
bus parking 291
Address translation, see Memory management unit
,
Addressing modes 89
,
Aligned data transfer 296
Alignment
,
data transfers 296
,
exception 170
,
misaligned accesses 82
,
rules 82
,
An (address bus) signals
APE (address parity error) signal
,
Arbitration, system bus 290
ARTRY (address retry) signal
B
,
BG (bus grant) signal 252
Block address translation
block address translation flow
,
definition 33
registers
,
description 61
,
initialization 196
selection of block address translation
Boundedly undefined, definition
,
BR (bus request) signal 251
,
Branch fall-through 226
,
Branch folding 226
Branch instructions
750gx_umIX.fm.(1.2)
March 27, 2006
,
262
,
285
,
300
,
285
,
300
254
,
294
,
301
,
263
,
285
,
189
,
186
,
87
,
285
IBM PowerPC 750GX and 750GL RISC Microprocessor
,
address calculation 106
condition register logical
,
list of instructions 107
, ,
system linkage 108 118
,
trap 108
, ,
Branch prediction 209 229
Branch processing unit
branch instruction timing
,
execution timing 225
latency, branch instructions
,
overview 30
Branch resolution
,
definition 209
,
resource requirements
BTIC (branch target instruction cache)
Burst data transfers
,
32-bit data bus 296
,
64-bit data bus 295
transfers with data delays, timing
Bus arbitration, see Data bus
,
Bus configurations 318
,
Bus interface unit (BIU) 122
Bus transactions and L1 cache
,
Byte ordering 89
C
Cache
,
arbitration 217
block instructions
dcbi, data cache block invalidate
dcbt, data cache block touch
,
block, definition 123
, ,
bus interface unit 122
cache operations
load/store operations, processor initiated
,
operations 136
,
overview 281
,
cache unit overview 123
cache-inhibited accesses (I bit)
,
characteristics 121
coherency
,
description 125
,
overview 142
reaction to bus operations
,
control instructions 131
,
bus operations 141
data cache configuration
,
dcbf/dcbst execution 328
,
hit 217
,
icbi 328
instruction cache configuration
instruction cache throttling
,
integration 122
L1 cache and bus transactions
User's Manual
,
107
,
231
,
238
237
,
216
,
314
,
279
,
139
,
119
,
116
279
,
130
,
125
,
143
,
123
,
124
,
347
,
139
Index
Page 369 of 377