Table 4-7. Settings Caused By Hard Reset - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and GL RISC Microprocessor

Table 4-7. Settings Caused by Hard Reset

Register
BATs Unknown
Cache, instruction
All blocks are unchanged from before
cache, and data
HRESET.
cache
CR All zeros
CTR 00000000
Breakpoint is disabled.
DABR
Address is unknown.
DAR 00000000
DEC FFFFFFFF
DSISR 00000000
FPRs Unknown
FPSCR 00000000
GPRs Unknown
HID0 00000000
HID1 00000000
IABR All zeros (break point disabled)
ICTC 00000000
L2CR 00000000
LR 00000000
Exceptions
Page 166 of 377
Setting
Register
MMCRn 00000000
MSR 00000040 (only IP set)
PMCn Unknown
PVR See the PowerPC 750GX Datasheet
Unknown (reservation flag
Reservation
Address
-cleared)
SDR1 00000000
SPRGs 00000000
SRR0 00000000
SRR1 00000000
SRs Unknown
Tag directory,
All entries are marked invalid, all LRU bits
instruction cache,
are set to zero, and caches are disabled.
and data cache
TBL 00000000
TBU 00000000
THRMn 00000000
TLBs Unknown
UMMCRn 00000000
UPMCn 00000000
USIA 00000000
XER 00000000
Setting
gx_04.fm.(1.2)
March 27, 2006