TLB Miss Latencies .............................................................................................................. 236
Branch Instructions .............................................................................................................. 238
Integer Instructions ............................................................................................................... 240
Data-Transfer Size ............................................................................................................... 259
Data-Bus Lane Assignments ................................................................................................ 266
Burst Ordering-64-Bit Bus .................................................................................................. 295
Burst Ordering-32-Bit Bus .................................................................................................. 296
Aligned Data Transfers ........................................................................................................ 296
Interpretation of LRU Bits ..................................................................................................... 324
Modification of LRU Bits ....................................................................................................... 325
ICTC Bit Field Settings ......................................................................................................... 348
Performance Monitor SPRs ................................................................................................. 350
750gx_umLOT.fm.(1.2)
March 27, 2006
IBM PowerPC 750GX and 750GL RISC Microprocessor
User's Manual
List of Tables
Page 17 of 377