IBM PowerPC 750GX User Manual page 144

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Table 3-5. Response to Snooped Bus Transactions
Snooped Transaction
Write-with-kill
Read
Read-with-intent-to-modify
(RWITM)
Write-with-flush-atomic
Reserved
Read-atomic
Read-with-intent-to-modify-
atomic
Reserved
Reserved
Instruction-Cache and Data-Cache Operation
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A write-with-kill operation is a burst transaction initiated due to a castout, caching-
enabled push, or snoop copy-back.
• If the address hits in the cache, the cache block is placed in the invalid (I) state
00110
(killing modified data that might have been in the block).
• If the address misses in the cache, no action is taken.
Any reservation associated with the address is canceled.
A read operation is used by most single-beat and burst load transactions on the bus.
For single-beat, caching-inhibited read transaction:
• If the addressed cache block is in the exclusive (E) state, the cache block
remains in the exclusive (E) state.
• If the addressed cache block is in the modified (M) state, the 750GX asserts
ARTRY and initiates a push of the modified block out of the cache, and the
cache block is placed in the exclusive (E) state.
01010 • If the address misses in the cache, no action is taken.
For burst read transactions:
• If the addressed cache block is in the exclusive (E) state, the cache block is
placed in the invalid (I) state.
• If the addressed cache block is in the modified (M) state, the 750GX asserts
ARTRY and initiates a push of the modified block out of the cache, and the
cache block is placed in the invalid (I) state.
• If the address misses in the cache, no action is taken.
A RWITM operation is issued to acquire exclusive use of a memory location for the
purpose of modifying it.
• If the addressed cache block is in the exclusive (E) state, the cache block is
placed in the invalid (I) state.
01110
• If the addressed cache block is in the modified (M) state, the 750GX asserts
ARTRY and initiates a push of the modified block out of the cache, and the
cache block is placed in the invalid (I) state.
• If the address misses in the cache, no action is taken.
Write-with-flush-atomic operations occur after the processor issues an stwcx.
instruction.
• If the addressed cache block is in the exclusive (E) state, the cache block is
placed in the invalid (I) state.
10010 • If the addressed cache block is in the modified (M) state, the 750GX asserts
ARTRY and initiates a push of the modified block out of the cache, and the
cache block is placed in the invalid (I) state.
• If the address misses in the cache, no action is taken.
Any reservation is canceled, regardless of the address.
10110 —
Read atomic operations appear on the bus in response to lwarx instructions and
11010
generate the same snooping responses as read operations.
The RWITM atomic operations appear on the bus in response to stwcx. instructions
11110
and generate the same snooping responses as RWITM operations.
00011 —
00111 —
750GX Response
gx_03.fm.(1.2)
March 27, 2006