IBM PowerPC 750GX User Manual page 247

Table 6-9. Load-and-Store Instructions
Instruction
Store Word with Update
Indexed
Store Word Indexed
TLB Invalidate Entry
1. For cache operations, the first number indicates the latency in finishing a single instruction; the second indicates the throughput for
back-to-back cache operations. Throughput might be larger than the initial latency, as more cycles might be needed to complete
the instruction to the cache, which stays busy keeping subsequent cache operations from executing.
2. The throughput number of six cycles for dcbz assumes it is to nonglobal (M = 0) address space. For global address space,
throughput is at least 11 cycles.
3. Load/store multiple/string instruction cycles are represented as a fixed number of cycles plus a variable number of cycles, where n
is the number of words accessed by the instruction.
gx_06.fm.(1.2)
March 27, 2006
(Page 4 of 4)
Primary
Mnemonic
Opcode
stwux 31
stwx 31
tlbie 31
IBM PowerPC 750GX and 750GL RISC Microprocessor
Extended
Unit
Opcode
183 LSU
151 LSU
306 LSU
User's Manual
Cycles Serialization
2:1 —
2:1 —
1
3:4 Execution
Instruction Timing
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