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User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
11.2.1 Performance-Monitor Registers
This section describes the registers used by the performance monitor.
11.2.1.1 Monitor Mode Control Register 0 (MMCR0)
The Monitor Mode Control Register 0 (MMCR0) is a 32-bit SPR provided to specify events to be counted and
recorded. MMCR0 can be written to only in supervisor mode. User-level software can read the contents of
MMCR0 by issuing an mfspr instruction to UMMCR0, described in Section 11.2.1.2 on page 351.
This register must be cleared at power up. Reading this register does not change its contents. MMCR0 can
be accessed with the mtspr and mfspr instructions using SPR 952.
For a diagram of this register and a description of its fields, see Monitor Mode Control Register 0 (MMCR0)
on page 72.
11.2.1.2 User Monitor Mode Control Register 0 (UMMCR0)
The contents of MMCR0 are reflected to UMMCR0, which can be read by user-level software. UMMCR0 can
be accessed with the mfspr instructions using SPR 936.
11.2.1.3 Monitor Mode Control Register 1 (MMCR1)
The Monitor Mode Control Register 1 (MMCR1) functions as an event selector for Performance-Monitor
Counter Registers 3 and 4 (PMC3 and PMC4). Corresponding events to the MMCR1 bits are described in
Section 11.2.1.5, Performance-Monitor Counter Registers (PMCn), on page 351.
MMCR1 can be accessed with the mtspr and mfspr instructions using SPR 956. User-level software can
read the contents of MMCR1 by issuing an mfspr instruction to UMMCR1, described in Section 11.2.1.4.
For a diagram of this register and a description of its fields, see Monitor Mode Control Register 1 (MMCR1)
on page 74.
11.2.1.4 User Monitor Mode Control Register 1 (UMMCR1)
The contents of MMCR1 are reflected to UMMCR1, which can be read by user-level software. UMMCR1 can
be accessed with the mfspr instructions using SPR 940.
11.2.1.5 Performance-Monitor Counter Registers (PMCn)
PMC1–PMC4 are 32-bit counters that can be programmed to generate interrupt signals when they overflow.
For a diagram of these registers and a description of the fields, see Performance-Monitor Counter Registers
(PMCn) on page 74.
Counters overflow when the high-order bit (the sign bit) becomes set; that is, they reach the value
2147483648 (0x8000_0000). However, an interrupt is not signaled unless both MMCR0[ENINT] and either
PMC1INTCONTROL or PMCINTCONTROL in the MMCR0 register are also set appropriately.
Note: The interrupts can be masked by clearing MSR[EE]. The interrupt signal condition might occur with
MSR[EE] cleared, but the exception is not taken until MSR[EE] is set. Setting MMCR0[DISCOUNT] forces
counters to stop counting when a counter interrupt occurs.
gx_11.fm.(1.2)
Performance Monitor and System Related Features
March 27, 2006
Page 351 of 377
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