Hardware-Implementation-Dependent Register 1 (Hid1) - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor

2.1.2.3 Hardware-Implementation-Dependent Register 1 (HID1)

The Hardware-Implementation-Dependent Register 1 (HID1) reflects the state of the PLL_CFG[0:4] signals.
HID1 can be accessed with mtspr and mfspr using SPR 1009.
PCE PRE
0 1 2 3 4 5 6
Bits Field Name
0:4 PCE
5:6 PRE
7 PSTAT1
8 ECLK
9:11 Reserved
12:13 Reserved
14 PI0
15 PS
16:20 PC0
21:22 PR0
23 Reserved
24:28 PC1
29:30 PR1
31 Reserved
Programming Model
Page 70 of 377
Reserved
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PLL external configuration bits (read-only).
PLL external range bits (read-only).
PLL status. Specifies the PLL clocking the processor:
0 PLL0 is the processor clock source
1 PLL1 is the processor clock source.
Set to 1 to enable the CLKOUT pin.
Select the internal clock to be output on the CLKOUT pin with the following decode:
000 Factory use only
001 PLL0 core clock (freq/2)
010 Factory use only
011 PLL1 core clock (freq/2)
100 Factory use only
101 Core clock (freq/2)
Other Reserved
Note: These clock configuration bits reflect the state of the PLL_CFG[0:4] pins. Clock
options should only be used for design debug and characterization.
Reserved.
PLL 0 internal configuration select.
0 Select external configuration and range bits to control PLL 0.
1 Select internal fields in HID1 to control PLL0.
PLL select.
0 Select PLL 0 as the source for the processor clock.
1 Select PLL 1 as the source for the processor clock.
PLL 0 configuration bits.
PLL 0 range select bits.
Reserved.
PLL 1 configuration bits.
PLL 1 range bits.
Reserved.
PS PC0 PR0
Description
PC1 PR1
gx_02.fm.(1.2)
March 27, 2006