IBM PowerPC 750GX User Manual page 210

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Fetch
Folding (branch folding) On the 750GX, a branch is expunged from (folded out of) the instruction queue via
Finish
Latency
Pipeline
Program order
Rename register
Reservation station
Retirement
Instruction Timing
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The process of bringing instructions from the system memory (such as a cache or
the main memory) into the instruction queue.
the dispatch mechanism, without being either passed to an execution unit or given
a position in the completion queue. Subsequent instructions are fetched from
sequential addresses for branches-not-taken and from target addresses for
branches-taken.
Finishing occurs in the last cycle of execution. (This could also be the first cycle of
execution for instructions that only require one cycle for execution.) In this cycle,
the output Rename Register and the completion queue entry are updated to indi-
cate that the instruction has finished executing.
The number of clock cycles necessary to execute an instruction and make ready
the results of that execution for a subsequent instruction.
In the context of instruction timing, the term 'pipeline' refers to the interconnection
of the stages. The events necessary to process an instruction are broken into
several cycle-length tasks to allow work to be performed on several instructions
simultaneously—analogous to an assembly line. As an instruction is processed, it
passes from one stage to the next. When it completes one stage, that stage
becomes available for the next instruction.
Although an individual instruction can take many cycles to complete (the number of
cycles is called instruction latency), pipelining makes it possible to overlap the
processing so that the throughput (number of instructions completed per cycle) is
greater than if pipelining were not implemented.
The order of instructions in an executing program. More specifically, this term is
used to refer to the original order in which program instructions are fetched into the
instruction queue from the system memory.
Temporary buffers used to hold either source or destination values for instructions
that are in a stage of execution. This simplifies the passing of data outside of the
General Purpose Register (GPR) file between instructions during execution.
A buffer between the dispatch and execution units where instructions await execu-
tion.
Removal of a completed instruction from the completion queue. At this time, any
output from the completed instruction is written to the appropriate architected desti-
nation register. This might be a GPR, a Floating Point Register (FPR), or a Condi-
tion Register (CR) field.
gx_06.fm.(1.2)
March 27, 2006