Mei Hardware Considerations; Figure 3-4. Mei Cache-Coherency Protocol-State Diagram (Wim = 001) - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Figure 3-4. MEI Cache-Coherency Protocol—State Diagram (WIM = 001)
RH
Bus Transactions
SH = Snoop Hit
RH = Read Hit
RM = Read Miss
WH = Write Hit
WM = Write Miss
SH/CRW = Snoop Hit, Cacheable Read/Write
Section 3.7, MEI State Transactions, on page 147 provides a detailed list of MEI transitions for various oper-
ations and WIM bit settings.

3.3.2.1 MEI Hardware Considerations

While the 750GX provides the hardware required to monitor bus traffic for coherency, the 750GX's data-
cache tags are single-ported, and a simultaneous load/store and snoop access represent a resource conflict.
In general, the snoop access has the highest priority and is given first access to the tags. The load or store
access will then occur on the clock following the snoop. The snoop is not given priority into the tags when the
snoop coincides with a tag write (for example, validation after a cache-block load). In these situations, the
snoop is retried and must rearbitrate before the lookup is possible.
Occasionally, cache snoops cannot be serviced and must be retried. These retries occur if the cache is busy
with a burst read or write when the snoop operation takes place.
Note that it is possible for a snoop to hit a modified cache block that is already in the process of being written
to the copy-back buffer for replacement purposes. If this happens, the 750GX retries the snoop, and raises
the priority of the castout operation to allow it to go to the bus before the cache-block fill.
Instruction-Cache and Data-Cache Operation
Page 128 of 377
Invalid
SH/CRW
WM
WH
Modified
SH
WH
SH/CRW
RM
Exclusive
SH/CIR
RH
Snoop Push
Cache Block Fill
gx_03.fm.(1.2)
March 27, 2006