Table 7-29: Crt A.c. Timing - Epson S1D13504 Technical Manual

Page 88
Symbol
DACCLK period
t1
DACCLK pulse width high
t2
DACCLK pulse width low
t3
data setup to DACCLK rising edge
t4
data hold from DACCLK rising edge
t5
HRTC cycle time
t6
HRTC pulse width (shown active low)
t7
t8
VRTC cycle time
t9
VRTC pulse width (shown active low)
t10
horizontal display period
t11
HRTC setup to DACCLK rising edge
VRTC falling edge to FPLINE falling edge
t12
phase difference
t13
BLANK# to DACCLK rising edge setup time
t14
BLANK# pulse width
t15
BLANK# falling edge to HRTC falling edge
t16
BLANK# hold from DACCLK rising edge
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t6 = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts
min
3. t7 = [((REG[07h] bits [3:0])+1)*8] Ts
min
4. t8 = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [6:0])+1)] lines
min
5. t9 = [((REG[0Ch] bits [2:0])+1)] lines
min
6. t10 = [((REG[04h] bits [6:0])+1)*8] Ts
min
7. t12 = [((REG[06h] bits [4:0])+1)*8] Ts
min
8. t14 = [((REG[04h] bits [6:0])+1)*8] Ts
min
9. t15 = [((REG[06h] bits [4:0])+1)*8 - 2] Ts
min
S1D13504
X19A-A-002-18

Table 7-29: CRT A.C. Timing

Parameter
Epson Research and Development
Min Typ Max
1
0.45
0.45
0.45
0.45
note 2
note 3
note 4
note 5
note 6
0.45
note 7
0.45
note 8
note 9
0.45
Hardware Functional Specification
Vancouver Design Center
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Issue Date: 01/01/30