It8368E Configuration - Epson S1D13504 Technical Manual

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5.3 IT8368E Configuration

S1D13504
X19A-G-012-04
The Generic MPU host interface control signals of the S1D13504 are asynchronous with
respect to the S1D13504 bus clock. This gives the system designer full flexibility in
choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether
both clocks should be the same and whether to use DCLKOUT (divided) as the clock
source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13504 clock frequencies.
The S1D13504 also has internal clock dividers providing additional flexibility.
The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E (or the first in
a two-IT8368E implementation) must have both "Fix Attribute/IO" and "VGA" modes on.
When both these modes are enabled, the MFIO pins provide control signals needed by the
S1D13504 host bus interface, and a 16M byte portion of the system PC Card attribute and
IO space is allocated to address the S1D13504. When accessing the S1D13504 the
associated card-side signals are disabled in order to avoid any conflicts.
Note
When a second IT8368E is used, it should not be set in VGA mode.
For mapping details, refer to Section 5.4, 'Memory Mapping and Aliasing" For further
information on configuring the IT8368E, refer to the IT8368E PC Card/GPIO Buffer Chip
Specification.
Epson Research and Development
Vancouver Design Center
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/02