Memory Configuration Registers; Table 8-2: Dram Refresh Rate Selection; Vancouver Design Center - Epson S1D13504 Technical Manual

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8.2.2 Memory Configuration Registers

Memory Configuration Register
REG[01h]
Refresh Rate
n/a
Bit 2
bits 6-4
Refresh Rate
Bits [2:0]
000
001
010
011
100
101
110
111
bit 2
bit 0
Hardware Functional Specification
Issue Date: 01/01/30
Refresh Rate Refresh Rate
Bit 1 Bit 0
DRAM Refresh Rate Select Bits [2:0]
These bits specify the amount of divide from the input clock (CLKI) to generate the DRAM refresh
clock rate, which is equal to 2

Table 8-2: DRAM Refresh Rate Selection

CLKI Divide Amount
64
128
256
512
1024
2048
4096
8192
WE# Control
When this bit = 1, 2-WE# DRAM is selected. When this bit = 0 2-CAS# DRAM is selected.
Memory Type
When this bit = 1, FPM-DRAM is selected. When this bit = 0, EDO-DRAM is selected.
This bit should be changed only when there are no read/write DRAM cycles. This condition occurs
when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled
(REG[1Bh] bit 0 = 1). For programming information, see S1D13504 Programming Notes and
Examples, document number X19A-G-002-xx.
n/a WE# Control
(ValueOfTheseBits + 6)
.
Refresh Rate for 33MHz
CLKI
520 kHz
260 kHz
130 kHz
65 kHz
33 kHz
16 kHz
8 kHz
4 kHz
Page 91
n/a Memory Type
DRAM Refresh
Time/256 Cycles
0.5 ms
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
S1D13504
X19A-A-002-18
RW