Epson S1D13504 Technical Manual page 345

Epson Research and Development
Vancouver Design Center
Pin # FPGA Signal
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Evaluation Board User Manual
Issue Date: 01/02/02
Table 3-2: Connector Pinout for Channel A7 (Continued)
S1D13504 Signal
chA7p4 N/C
chA7p5 N/C
chA7p6 N/C
chA7p7 N/C
chA7p8 N/C
chA7p9 N/C
chA7p10 N/C
ib1 N/C
ib2 N/C
ib3 N/C
ib4 N/C
ib5 N/C
ib6 N/C
ib7 N/C
ib8 N/C
GND GND
GND GND
Channel A7
Pin #
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FPGA Signal S1D13504 Signal
GND GND
dc3v DC3V
GND GND
dc3vs N/C
GND GND
dc12v DC12V
GND GND
battery N/C
GND GND
dcXA N/C
base5vDc N/C
dcXB N/C
GND GND
dcXC N/C
GND GND
senseH N/C
senseL N/C
S5U13504-D9000
X19A-G-003-05
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