Epson S1D13504 Technical Manual page 375

Color graphics lcd/crt controller

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Epson Research and Development

Vancouver Design Center

PR31500/PR31700

LHA23/MFIO10

Notes: The Chip Select Logic shown above is necessary to guarantee timing parameter t1 of the Generic MPU Interface

Asynchronous Timing (for details refer to the S1D13504 Hardware Functional Specification , document number

X19A-A-002-xx).

When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that may reset

the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

Figure 5-1: S1D13504 to PR31500/PR31700 Connection using One IT8368E

Interfacing to the Philips MIPS PR31500/PR31700 Processor

Issue Date: 01/02/02

Clock divider

For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping".

System RESET

X19A-G-005-08

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