Pal Equations; Register/Memory Mapping - Epson S1D13504 Technical Manual

Page 14

4.3 PAL Equations

CHIP PCCAPP PAL16L8
PIN 1 /oe
PIN 2 /we
PIN 3 /ce1
PIN 4 /ce2
PIN 5 /pcreg
PIN 6 breset
PIN 12 /we0
PIN 13 /we1
PIN 14 /cs
PIN 15 /rd0
PIN 16 /rd1
PIN 17 /reset
PIN 10 gnd
PIN 20 vcc
EQUATIONS
rd0 = oe * ce1 * /pcreg
rd1 = oe * ce2 * /pcreg
we0 = we * ce1 * /pcreg
we1 = we * ce2 * /pcreg
cs = rd0 + rd1 + we0 + we1
reset = breset

4.4 Register/Memory Mapping

S1D13504
X19A-G-009-05
The PAL equations used for the implementation presented in this document are as follows.
Note that PALASM syntax uses positive logic. Active low pins are inverted in the pin
declaration section.
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
The S1D13504 is a memory mapped device. The internal registers are mapped in the lower
PC Card memory address space starting at zero. The display buffer requires 2M bytes and
is mapped in the third and fourth megabytes of the PC Card memory address space (ranging
from 200000h to 3fffffh).
The PC Card socket provides 64M bytes of address space. Without further resolution on
the decoding logic (M/R# connected to A21), the entire register set is aliased for every 64
byte boundary within the specified address range above. Since address bits A[25:22] are
ignored, the S1D13505 registers and display buffer are aliased 16 times.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.
; bus read enable
; bus write enable
; bus low byte enable
; bus high byte enable
; bus CIS cycle enable
; bus reset (active high)
; S1D13504 low byte write
; S1D13504 high byte write
; S1D13504 chip select
; S1D13504 low byte read
; S1D13504 high byte read
; S1D13504 reset
; supply
; supply
; /pcreg means disable in attribute mode
; /pcreg means disable in attribute mode
; /pcreg means disable in attribute mode
; /pcreg means disable in attribute mode
; inversion appears in pin declaration section
Epson Research and Development
Vancouver Design Center
Interfacing to the PC Card Bus
Issue Date: 01/02/02