Epson S1D13504 Technical Manual page 101

Epson Research and Development
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Vertical Non-Display Period Register
REG[0Ah]
Vertical
Non-Display
n/a
Period Status
(RO)
bit 7
Note
bits 5-0
Note
VRTC/FPFRAME Start Position Register
REG[0Bh]
n/a n/a
bits 5-0
Note
Hardware Functional Specification
Issue Date: 01/01/30
Vertical Vertical
Non-Display Non-Display
Period Bit 5 Period Bit 4
Vertical Non-Display Period Status
This is a read-only status bit. A "1" indicates that a vertical non-display period is occurring. A "0"
indicates that display output is in a vertical display period.
When configured for a dual panel, this bit will toggle at twice the frame rate.
Vertical Non-Display Period Bits [5:0]
These bits specify the vertical non-display period height in 1-line resolution.
Vertical non-display period height in number of lines = (ContentsOfThisRegister) + 1.
The maximum vertical non-display period height is 64 lines.
This register must be programmed such that
REG[0Ah] 1 and (REG[0Ah] bits [5:0] + 1)
VRTC/ VRTC/
FPFRAME FPFRAME
Start Position Start Position
Bit 5 Bit 4
VRTC/FPFRAME Start Position Bits [5:0]
For CRTs and TFTs, these bits specify the delay in lines from the start of the vertical non-display
period to the leading edge of the VRTC pulse and FPFRAME pulse respectively. For passive LCDs,
FPFRAME is automatically created and these bits have no effect.
VRTC/FPFRAME start position (lines) = VRTC/FPFRAME Start Position Bits [5:0] + 1.
The maximum VRTC start delay is 64 lines.
This register must be programmed such that
(REG[0Ah] bits [5:0] + 1)
Vertical Vertical
Non-Display Non-Display
Period Bit 3 Period Bit 2
(REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
VRTC/ VRTC/
FPFRAME FPFRAME
Start Position Start Position
Bit 3 Bit 2
(REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
Page 95
RW
Vertical Vertical
Non-Display Non-Display
Period Bit 1 Period Bit 0
RW
VRTC/ VRTC/
FPFRAME FPFRAME
Start Position Start Position
Bit 1 Bit 0
S1D13504
X19A-A-002-18