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Epson Research and Development
Vancouver Design Center
Symbol
t1
Clock period
t2
Clock pulse width high
t3
Clock pulse width low
t4
A[20:0], M/R#, RD/WR# setup to CKIO
t5
A[20:0], M/R#, RD/WR# hold from CS#
t6
BS# setup
t7
BS# hold
t8
CSn# setup
2
t9
Falling edge RD# to D[15:0] driven
t10
Rising edge CSn# to WAIT# tri-state
1
t11
Falling edge CSn# to WAIT# driven
t12
CKIO to WAIT# delay
t13
D[15:0] setup to first CKIO after BS# (write cycle)
t14
D[15:0] hold (write cycle)
t15
D[15:0] valid to WAIT# rising edge (read cycle)
t16
Rising edge RD# to D[15:0] tri-state (read cycle)
Hardware Functional Specification
Issue Date: 01/01/30
Table 7-1: SH-3 Interface Timing
Parameter
1.
If the S1D13504 host interface is disabled, the timing for WAIT# driven is relative to the fall-
ing edge of CSn# or the first positive edge of CKIO after A[20:0] and M/R# become valid,
whichever occurs later.
2.
If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of RD# or the first positive edge of CKIO after A[20:0] and M/R# become valid,
whichever occurs later.
Min
Max
Units
25
ns
5
ns
5
ns
4
ns
0
ns
3
ns
0
ns
0
ns
3
ns
0
4
ns
1
11
ns
3
15
ns
0
ns
0
ns
0
ns
2
9
ns
S1D13504
X19A-A-002-18
Page 37
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