Table 7-3: Mc68K Bus 2 Interface Timing - Epson S1D13504 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
t1
Clock period
t2
Clock pulse width high
t3
Clock pulse width low
A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0 AS# =
t4
0, and either UDS#=0 or LDS# = 0
t5
A[20:0], SIZ[1:0], M/R# hold from AS#
t6
CS# hold from AS#
t7
R/W# setup to DS#
t8
R/W# hold from AS#
1
t9
AS# = 0 and CS# = 0 to DSACK1# driven high
t10
AS# high to DSACK1# high impedance
D[31:16] valid to second CLK where CS# = 0 AS# = 0, and
t11
either UDS#=0 or LDS# = 0 (write cycle)
t12
D[31:16] hold from falling edge of DSACK1# (write cycle)
Falling edge of UDS# = 0 or LDS# = 0 to D[31:16] driven (read
2
t13
cycle)
t14
D[31:16] valid to DSACK1# falling edge (read cycle)
UDS# and LDS# high to D[31:16] invalid/high impedance (read
t15
cycle)
t16
AS# high setup to CLK
Hardware Functional Specification
Issue Date: 01/01/30

Table 7-3: MC68K Bus 2 Interface Timing

Parameter
1. If the S1D13504 host interface is disabled, the timing for DSACK1# driven high is relative to
the falling edge of AS# or the first positive edge of CLK after A[20:0] and M/R# become
valid, whichever occurs later.
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# becomes
valid, whichever occurs later.
Min Max Units
30 ns
5 ns
5 ns
4 ns
0 ns
0 ns
5 ns
0 ns
1 ns
1 5 ns
0 ns
0 ns
3 ns
0 ns
2 11 ns
3 ns
S1D13504
X19A-A-002-18
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