Re-Programming Registers; Disabling The Half Frame Buffer Sequence - Epson S1D13504 Technical Manual

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REG[20h] = 0x00
REG[21h] = 0x00
REG[24h] = 0x00
for (index = 0; index < 16; ++index) {
}
REG[27h] = 0x00
REG[23h] = 0x10
REG[0Dh] = 0x09

2.2.3 Re-Programming Registers

2.3 Disabling the Half Frame Buffer Sequence:

Programming Notes and Examples
Issue Date: 01/02/01
Table 2-1: Initializing the S1D13504 Registers (Continued)
REG[26h] = RED[index];
REG[26h] = GREEN[index];
REG[26h] = BLUE[index];
The only register which may require modification after the initialization sequence is the Half Frame
Buffer. The Memory Type, DUAL/SINGLE, and the Performance Register bits should never be
modified after initialization.
The Half Frame Buffer can be ENABLED asynchronously.
To DISABLE the Half Frame Buffer, do the following:
1. Disable the display FIFO REG[23] bit 7=1.
2. Set the horizontal resolution to 0 (REG[04]=0).
Setting the horizontal resolution = 0 will shut-off any Half Frame Buffer DRAM accesses
within 1024 PCLK's or less (1024 PCLK's is the worst case)
3. Wait for VNDP 1->0->1 transitions (REG[0A] bit 7).
Waiting for 1 FRAME delay will guarantee that the Half Frame Buffer is idle.
4. Disable the Half Frame Buffer (REG[1B] bit 0=1).
5. Re-program the horizontal resolution to your original value.
General I/O Control
Look-Up Table Address
Update Look-Up Table based on the
RED[16], GREEN[16], and BLUE[16]
tables defined earlier in your
program.
Look-Up Table Bank Select
Enable the Display FIFO
Enable Display
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S1D13504
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