Epson S1D13504 Technical Manual page 411

Color graphics lcd/crt controller
Hide thumbs Also See for S1D13504:
Table of Contents

Advertisement

Epson Research and Development
Vancouver Design Center
SIZ[1:0], TT[1:0]
SIZ[1:0], TT[1:0]
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor
Issue Date: 01/02/02
The following figure illustrates a typical memory read cycle on the MCF5307 system bus.
BCLK0
TS
TA
TIP
A[31:0]
R/W
D[31:0]
Transfer Start
Wait States
Figure 2-1: MCF5307 Memory Read Cycle
The following figure illustrates a typical memory read cycle on the MCF5307 system bus.
BCLK0
TS
TA
TIP
A[31:0]
R/W
D[31:0]
Transfer Start
Figure 2-2: MCF5307 Memory Write Cycle
Transfer
Complete
Valid
Wait States
Transfer
Complete
Sampled when TA low
Next Transfer
Starts
Next Transfer
Starts
Page 9
S1D13504
X19A-G-011-07

Advertisement

Table of Contents
loading

Table of Contents