Generic Mpu Host Bus Interface Signals - Epson S1D13504 Technical Manual

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3.2 Generic MPU Host Bus Interface Signals

S1D13504
X19A-G-005-08
The interface requires the following signals:
• BUSCLK is a clock input which is required by the S1D13504 host bus interface. It is
separate from the input clock (CLKI) and is typically driven by the host CPU system
clock.
• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the CPU
address and data bus, respectively. The hardware engineer must ensure that MD4 selects
the proper endian mode upon reset.
• M/R# (memory/register) may be considered an address line, allowing system address
A21 to be connected to the M/R# line.
• Chip Select (CS#) must be driven low whenever the S1D13504 is accessed by the host
CPU.
• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is writing data to the S1D13504. These signals
must be generated by external hardware based on the control outputs from the host CPU.
• RD# (RD0#) and RD/WR# (RD1#) are read enables for the low-order and high-order
bytes, respectively, to be driven low when the host CPU is reading data from the
S1D13504. These signals must be generated by external hardware based on the control
outputs from the host CPU.
• WAIT# is a signal output from the S1D13504 that indicates the host CPU must wait
until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU
accesses to the S1D13504 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the S1D13504 internal registers and/or display
buffer. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete.
• The Bus Start (BS#) signal is not used for the Generic MPU host bus interface and
should be tied low (connected to GND).
Epson Research and Development
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Vancouver Design Center
Issue Date: 01/02/02