Epson S1D13504 Technical Manual page 119

Epson Research and Development
Vancouver Design Center
RAMDAC Palette Data Register
REG[2Eh] or REG[2Fh]
RAMDAC RAMDAC
Data Bit 7 Data Bit 6
bits 7-0
Hardware Functional Specification
Issue Date: 01/01/30
RAMDAC RAMDAC
Data Bit 5 Data Bit 4
RAMDAC Palette Data Bits [7:0]
A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 0
and DACRS0 = 1 to the external RAMDAC for a palette data register access. The RAMDAC data
must be transferred directly between the system data bus and the external RAMDAC through either
data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
RAMDAC RAMDAC
Data Bit 3 Data Bit 2
Page 113
RW
RAMDAC RAMDAC
Data Bit 1 Data Bit 0
S1D13504
X19A-A-002-18