Epson S1D13504 Technical Manual page 293

Epson Research and Development
Vancouver Design Center
Comments
Windows® CE Display Drivers
Issue Date: 01/02/01
• Some of the D9000 systems may not be able to provide enough current for your LCD panel to
operate properly. If this is the case, an external power supply should be connected to the panel.
• The Seiko Epson Common Interface FPGA code assumes the display buffer starts at
0x12200000 and IO starts at 0x12000000. If the display buffer or IO location is modified, the
corresponding entries in the file S1D13504.H have to be changed. S1D13504.H is located in
X:\wince\platform\odo\drivers\display\S1D13504 (where X: is the drive letter).
• The External RAMDAC is decoded at the even addresses on a little-endian system. The
RAMDAC registers are mapped as follows:
• RAMDAC Pixel Read Mask Register is REG[28h]
• RAMDAC Read Mode Address Register is REG[2Ah]
• RAMDAC Write Mode Address Register is REG[2Ch]
• RAMDAC Palette Data Register is REG[2Eh]
• The driver is CPU independent but will require another ODO.RBF file to support other CPUs
when running on the Hitachi D9000 or ETMA ODO platform. Please check with Seiko Epson for
the latest supported CPU ODO files.
• As the time of this printing, the drivers have been tested on the SH-3 and x86 CPUs and have
only been run with v2.0 of the ETK. We are constantly updating the drivers so please check our
website at www.erd.epson.com, or contact your Seiko Epson or Epson Electronics America sales
representative.
Page 9
S1D13504
X19A-E-001-04