Epson S1D13504 Technical Manual page 459

Color graphics lcd/crt controller

Hide thumbs Also See for S1D13504:

Table of Contents

Epson Research and Development

Vancouver Design Center

Interfacing to the Motorola MPC821 Microprocessor

Issue Date: 01/02/02

MPC8BUG does not support comments or symbolic equates; these have been added for

It is important to note that when the MPC821 comes out of reset, its on-chip caches and

MMU are disabled. If the data cache is enabled, the MMU must be setup so the

S1D13504 memory block is tagged as non-cacheable. This ensures that accesses to the

S1D13504 will occur in proper order, and the MPC821 will not attempt to cache any

data read from or written to the S1D13504 or its display buffer.

X19A-G-010-05

Chapters

Table of Contents