Epson S1D13504 Technical Manual page 196

Page 58
/*
** Register 6: HRTC/FPLINE Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x06) = 0x00;
/*
** Register 7: HRTC/FPLINE Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x07) = 0x00;
/*
** Registers 8-9: Vertical Display Height (VDP) - 240 lines.
**
*/
*(pRegs + 0x08) = 0xEF;
*(pRegs + 0x09) = 0x00;
/*
** Register A: Vertical Non-Display Period (VNDP)
**
**
**
*/
*(pRegs + 0x0A) = 0x01;
/*
** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x0B) = 0x00;
/*
** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x0C) = 0x00;
/*
** Registers E-F: Screen 1 Line Compare - unless setting up for
**
*/
*(pRegs + 0x0E) = 0xFF;
*(pRegs + 0x0F) = 0x03;
/*
** Registers 10-12: Screen 1 Display Start Address - start at the
**
*/
*(pRegs + 0x10) = 0x00;
*(pRegs + 0x11) = 0x00;
*(pRegs + 0x12) = 0x00;
/*
** Register 13-15: Screen 2 Display Start Address - not applicable
**
*/
*(pRegs + 0x13) = 0x00;
*(pRegs + 0x14) = 0x00;
*(pRegs + 0x15) = 0x00;
S1D13504
X19A-G-002-07
240 - 1 = 239t = 0xEF
This register must be programed with register 5 (HNDP)
to arrive at the frame rate closest to the desired
frame rate.
split screen operation use 0x3FF.
first byte in display memory.
unless setting up for split screen operation.
Epson Research and Development
/* 0000 0000 */
/* 0000 0000*/
/* 1110 1111 */
/* 0000 0000 */
/* 0000 0001 */
/* 0000 0000 */
/* 0000 0000 */
/* 1111 1111 */
/* 0000 0011 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
Vancouver Design Center
Programming Notes and Examples
Issue Date: 01/02/01