Dual Color 8-Bit Panel Timing; Figure 7-33: Dual Color 8-Bit Panel Timing; Vancouver Design Center - Epson S1D13504 Technical Manual

Epson Research and Development

Vancouver Design Center

7.4.10 Dual Color 8-Bit Panel Timing

FPFRAME
FPLINE
MOD
UD[3:0], LD[3:0]
FPLINE
MOD
FPSHIFT
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 01/01/30
VDP
LINE 1/241 LINE 2/242
HDP
1-G 2 1-G6
1-R 1 1-B3 1-R5
1-R4
1-B2 1-G5 1-B6
1-G1
1-R 3 1-R7
1-B1 1-G4 1-B5
1-R2 1-G3 1-R6
1-B4 1-G7
241-R 1 241-G2 241-B 3 241-R5 241-G6
241-G1 24 1-B2 241-R 4 241-G 5 241-B6
241-G4 241-B5
241-B1 241-R3 241-R7
241-R 2 241-G3 241-B4 241-R 6 241-G7

Figure 7-33: Dual Color 8-Bit Panel Timing

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
VNDP
LINE 239/479 LINE 240/480
1-B7
1-R8
1-G8
1-B8
241-B7
241-R8
241-G8
241-B8
Page 79
LINE 1/241
HNDP
1-B639
1-R640
1-G640
1-B640
2 41-
B639
241-
R640
241-
G640
241-
B640
S1D13504
X19A-A-002-18