External Ramdac Read / Write Timing; Table 7-30: Generic Bus Ramdac Read / Write Timing; Figure 7-41: Generic Bus Ramdac Read / Write Timing; Vancouver Design Center - Epson S1D13504 Technical Manual

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Vancouver Design Center

7.4.14 External RAMDAC Read / Write Timing

Read
AB[20:0]
CS#
M/R#
DACRS[1:0]
Valid RD# Command
(depends on CPU bus)
DACRD#
Write
Valid WR# command
(depends on CPU bus)
DACWR#
Symbol
T
Bus clock period
BCLK
t1
AB[20:0], CS#, M/R# delay to DACRS[1:0]
t2
DACRS[1:0] hold from AB[20:0], CS#, M/R# negated
t3
Valid RD# command to DACRS[1:0] delay
t4
DACRD# hold from valid RD# command negated
t5
Valid WR# command to DACWR# delay
t6
DACWR# pulse width low
Hardware Functional Specification
Issue Date: 01/01/30
t1
t3
t5

Figure 7-41: Generic Bus RAMDAC Read / Write Timing

Table 7-30: Generic Bus RAMDAC Read / Write Timing

Parameter
t6
Min Typ
30
8
3
2 T
BCLK
2.45 T
BCLK
Page 89
t2
t4
Max Units
ns
10 ns
10 ns
33 ns
14 ns
ns
2.55 T ns
BCLK
S1D13504
X19A-A-002-18