Table 8-11: Minimum Memory Timing Selection - Epson S1D13504 Technical Manual

Page 108
Performance Enhancement Register 0
REG[22h]
EDO Read- RC Timing
Write Delay Value Bit 1
bit 7
bits 6-5
REG[22h] Bits [6:5]
bit 4
S1D13504
X19A-A-002-18
RC Timing RAS# to
Value Bit 0 CAS# Delay
Note
Changing this register to non-zero value, or to a different non-zero value, should be done only
when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO
is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For
programming information, see S1D13504 Programming Notes and Examples, document number
X19A-G-002-xx.
EDO Read-Write Delay
This bit is used for EDO-DRAM to select the delay during the read-write transition. A "0" selects 2
MCLK delay for the read-write transition. A "1" selects 1 MCLK delay for the read-write DRAM.
This bit has no effect for FPM-DRAM which always uses 1 MCLK delay for the read-write transi-
tion. This bit may be programmed to 1 when the MCLK frequency is less than 30MHz.
RC Timing Value (N ) Bits [1:0]
RC
These bits select the DRAM random-cycle timing parameter, t
(N ) of MCLK periods (T
RC
t , the RAS pulse width. Use the following two formulae to calculate N
RAS
value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
N = Round-Up (t
RC
N = Round-Up (t
RC
= Round-Up (t
The resulting t is related to N
RC
t = (N ) T
RC RC

Table 8-11: Minimum Memory Timing Selection

00
01
10
11
RAS# to CAS# Delay (N
RCD
This bit selects the DRAM RAS# to CAS# delay parameter, t
(N ) of MCLK periods (T
RCD
access time, t . Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
RAC
N = Round-Up((t
RCD
= 2
= Round-Up(t
RAC
= Round-Up(t
RAC
RAS# RAS#
Precharge Precharge
Timing Bit 1 Timing Bit 0
) used to create t . N
M RC RC
/T )
RC M
/T + N )
RAS M RP
/T + 1.55)
RAS M
as follows:
RC
M
N
RC
5
4
3
Reserved
)
) used to create t . N
M RCD
+ 5)/T - 1) if EDO and N
RAC M
if EDO and N
/T - 1) if FPM and N
M
/T - 0.45) if FPM and N
M
Epson Research and Development
Vancouver Design Center
n/a
. These bits specify the number
RC
should be chosen to meet t
then choose the larger
RC
if N = 1 or 2
RP
if N = 1.5
RP
Minimum Random Cycle
Width ( t )
RC
5 T
M
4 T
M
3 T
M
Reserved
. This bit specifies the number
RCD
must be chosen to satisfy the RAS#
RCD
= 1 or 2
RP
= 1.5
RP
= 1 or 2
RP
= 1.5
RP
Hardware Functional Specification
Issue Date: 01/01/30
RW
Reserved
as well as
RC