Interfacing To The Mcf5307; The Mcf5307 System Bus; Overview; Normal (Non-Burst) Bus Transactions - Epson S1D13504 Technical Manual

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2 Interfacing to the MCF5307

2.1 The MCF5307 System Bus

2.1.1 Overview

2.1.2 Normal (Non-Burst) Bus Transactions

S1D13504
X19A-G-011-07
The MCF5200/5300 family of processors feature a high-speed synchronous system bus
typical of modern microprocessors. This section provides an overview of the operation of
the MCF5307 bus in order to establish interface requirements.
The MCF5307 microprocessor family uses a synchronous address and data bus, very
similar in architecture to the MC68040 and MPC8xx. All outputs and inputs are timed with
respect to a square-wave reference clock called BCLK0 (Master Clock). This clock runs at
a software-selectable divisor rate from the machine cycle speed of the CPU core, typically
20 to 33 MHz. Both the address and the data bus are 32 bits in width. All IO accesses are
memory-mapped; there is no separate IO space in the MCF5307 architecture.
The bus can support two types of cycle, normal and burst. Burst memory cycles are used to
fill on-chip cache memories, and for certain on-chip DMA operations. Normal cycles are
used for all other data transfers.
The bus master initiates a data transfer by placing the memory address on address lines A31
through A0 and driving TS (Transfer Start) low for one clock cycle. Several control signals
are also provided with the memory address:
• SIZ[1:0] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32 bits in width.
• R/W -- set high for read cycles and low for write cycles.
• TT[1:0] (Transfer Type Signals) -- provides more detail on the type of transfer being
attempted.
• TIP (Transfer In Progress) -- asserts whenever a bus cycle is active.
When the peripheral device being accessed has completed the bus transfer, it asserts TA
(Transfer Acknowledge) for one clock cycle, completing the bus transaction. Once TA has
been asserted, the MCF5307 will not start another bus cycle until TA has been de-asserted.
The minimum length of a bus transaction is two bus clocks.
Epson Research and Development
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor
Vancouver Design Center
Issue Date: 01/02/02