Epson Research and Development
Vancouver Design Center
4 Block Description
4.1 Functional Block Diagram
Register
Host
CPU / MPU
Bus Clock
4.2 Functional Block Descriptions
4.2.1 Host Interface
4.2.2 Memory Controller
4.2.3 Display FIFO
Hardware Functional Specification
Issue Date: 01/01/30
16-bit FPM/EDO
Memory
Controller
CPU
R/W
I/F
Memory Clock
Figure 4-1: System Block Diagram Showing Datapaths
The Host Interface block provides the means for the CPU/MPU to communicate with the display
buffer and internal registers, via one of the supported bus interfaces.
The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well
as generates the necessary signals to interface to one of the supported 16-bit memory devices (FPM-
DRAM or EDO-DRAM).
The Display FIFO block fetches display data from the Memory Controller for display refresh.
DRAM
Power Save
Clocks
Display
FIFO
Pixel Clock
LCD
I/F
Look-Up
Table
CRTC
Page 17
LCD
DAC
Data
DAC
Control
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