Table 7-27: Dual Color 16-Bit Panel A.c. Timing; Figure 7-36: Dual Color 16-Bit Panel A.c. Timing - Epson S1D13504 Technical Manual

Page 82
Sync Timing
Data Timing
Symbol
t1
FPFRAME setup to FPLINE falling edge
t2
FPFRAME hold from FPLINE falling edge
t3
FPLINE period
t4
FPLINE pulse width
t5
MOD transition to FPLINE falling edge
t6
FPSHIFT falling edge to FPLINE rising edge
t7
FPSHIFT falling edge to FPLINE falling edge
t8
FPLINE falling edge to FPSHIFT falling edge
t9
FPSHIFT period
t10
FPSHIFT pulse width low
t11
FPSHIFT pulse width high
t12
UD[7:0], LD[7:0] setup to FPSHIFT falling edge
t13
UD[7:0], LD[7:0] hold to FPSHIFT falling edge
t14
FPLINE falling edge to FPSHIFT rising edge
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1 = t3 - 9Ts
min min
3. t3 = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
min
4. t5 = [((REG[04h] bits [6:0])+1)*8 - 1] Ts
min
5. t6 = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts
min
6. t7 = [((REG[05h] bits [4:0]) + 1)*8 - 9] Ts
min
S1D13504
X19A-A-002-18
FPFRAME
FPLINE
MOD
FPLINE
FPSHIFT
UD[7:0]
LD[7:0]

Figure 7-36: Dual Color 16-Bit Panel A.C. Timing

Table 7-27: Dual Color 16-Bit Panel A.C. Timing

Parameter
t1 t2
t4
t5
t6
t8
t7 t14
t12
Epson Research and Development
Vancouver Design Center
t3
t9
t11 t10
t13
1 2
Min Typ Max
note 2
9
note 3
9
33 note 4
note 5
note 6
t14 + 2
2
1
1
1
1
10
Hardware Functional Specification
Issue Date: 01/01/30
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts