Gpio Ttl Output Timing (Trigger Overlap = Off, Timed Mode) - IAI SP-20000M-PMCL User Manual

SP-20000-PMCL User Manual (Ver. 3.1)

GPIO TTL Output Timing (Trigger Overlap = Off, Timed Mode)

GPIO TTL Out Timing
GPIO Out Timing (Reference) (80 MHz, EPS Trigger, Trigger Overlap= OFF)
Description
Frame Start Trigger to Frame
(a)
Trigger Wait Falling Edge
Exposure Active Falling Edge
(b)
to FVAL Raising Edge
Frame Active Falling Edge to
(c) Frame Trigger Wait Raising
Edge
(d) Exposure Active
(e) FVAL Active
Tap Geometry Setting
1X8-1Y 1X4-1Y 1X2-1Y
820 ns 820 ns 1.010 us Frame Start Trigger is input through TTL IN 1
320 us 328 us 656 us
(320 us) (328 us) (656 us)
1.00 us 1.00 us 1.00 us
8.91 us 8.91 us 8.98 us
(10.26 (10.26 (10.31
us) us) us)
31.42 62.84 125.69
ms ms ms
- 78 -
Varies by Tap Geometry setting. ( ) is Exposure Active which
is assigned to Camera Link Spare Bit
If Exposure Time is 10, ( ) is Exposure Active which is
assigned to Camera Link Spare Bit
If Binning off and [Height]=3840, (Will be changed by Height
setting)
Main Functions
Note