Table of Contents
Advertisement
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B.
Bit
PB DDR
Initial value
Read/Write
A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input pin
if this bit is cleared to 0.
Bit 6 is reserved.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a PBDDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores data for
pins PB
, PB
to PB
7
5
0
Bit
Initial value
Read/Write
R/W
When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is
returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin
level is read. Bit 6 is reserved. Bit 6 can be written and read, but cannot be used for a port input or
output.
If bit 6 in PBDDR is read while its value is 1, the value of bit 6 in PBDR will be read directly. If
bit 6 in PBDDR is read while its value is 0, it will always be read as 1.
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
7
6
—
PB DDR
7
0
0
W
W
Reserved bit
.
7
6
PB
—
7
0
0
R/W
R/W
Reserved bit
5
4
PB DDR
PB DDR
5
4
3
0
0
W
W
Port B data 7, 5 to 0
These bits select input or output for port B pins
5
4
PB
PB
PB
5
4
0
0
R/W
R/W
Port B data 7, 5 to 0
These bits store data for port B pins
3
2
PB DDR
PB DDR
2
1
0
0
W
W
3
2
PB
PB
3
2
0
0
R/W
R/W
1
0
PB DDR
0
0
0
W
W
1
0
PB
1
0
0
0
R/W
177
Advertisement
Table of Contents
