Table of Contents
Advertisement
Table 1-3 Pin Functions (cont)
Type
Symbol
RES
System
control
RESO/
FWE
STBY
Interrupts
NMI
IRQ
, IRQ
5
IRQ
, IRQ
1
Address bus A
to A
23
A
to A
19
A
to A
7
Data bus
D
to D
7
AS
Bus control
RD
WR
WAIT
16-bit
TCLKD to
TCLKA
integrated
timer unit
TIOCA
TIOCA
(ITU)
TIOCB
TIOCB
TOCXA
TOCXB
12
Pin No.
48
57
47
49
72, 11,
4
69, 68
0
,
77 to 80,
20
,
42 to 31,
8
29 to 22
0
20 to 13
0
54
55
56
43
76 to 73
3, 1, 79,
to
4
77, 75
0
4, 2, 80,
to
4
78, 76
0
5
4
6
4
I/O
Name and Function
Input
Reset input: When driven low, this pin
resets the chip
Output/
Reset output (Masked ROM version):
Input
Outputs WDT-generated reset signal to an
external device.
Write enable signal (F-ZTAT version):
Flash memory write control signal.
Input
Standby: When driven low, this pin forces a
transition to hardware standby mode
Input
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Input
Interrupt request 5, 4, 1, 0: Maskable
interrupt request pins
Output
Address bus: Outputs address signals
Input/
Data bus: Bidirectional data bus
output
Output
Address strobe: Goes low to indicate valid
address output on the address bus
Output
Read: Goes low to indicate reading from the
external address space.
Output
Write: Goes low to indicate writing to the
external address space indicates valid data
on the data bus.
Input
Wait: Requests insertion of wait states in
bus cycles during access to the external
address space
Input
Clock input A to D: External clock inputs
Input/
Input capture/output compare A4 to A0:
Output
GRA4 to GRA0 output compare or input
capture, or PWM output
Input/
Input capture/output compare B4 to B0
output
GRB4 to GRB0 output compare or input
capture, or PWM output
Output
Output compare XA4: PWM output
Output
Output compare XB4: PWM output
Advertisement
Table of Contents
