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Table 18-6 Timing of On-Chip Supporting Modules
Condition A:
V
CC
MHz, T
range specifications)
Condition B:
V
CC
MHz, T
range specifications)
Condition C:
V
CC
MHz, T
range specifications)
Item
ITU
Timer output delay
time
Timer input setup
time
Timer clock input
setup time
Timer
Single edge
clock
pulse
Both edges
width
SCI
Input
Asynchro-
nous
clock
cycle
Synchro-
nous
Input clock rise time
Input clock fall time
Input clock pulse
width
530
= 2.7 V to 5.5 V, AV
= –20°C to +75°C (regular specifications), T
a
= 3.0 V to 5.5 V, AV
= –20°C to +75°C (regular specifications), T
a
= 5.0 V ± 10%, AV
CC
= –20°C to +75°C (regular specifications), T
a
Condition A
8 MHz
Symbol
Min
t
—
TOCD
t
50
TICS
t
50
TCKS
t
1.5
TCKWH
t
2.5
TCKWL
t
4
Scyc
6
t
—
SCKr
t
—
SCKf
t
0.4
SCKW
= 2.7 V to 5.5 V, V
CC
= 3.0 V to 5.5 V, V
CC
= 5.0 V ± 10%, V
SS
Condition B
10 MHz
Max
Min
Max
100
—
100
—
50
—
—
50
—
—
1.5
—
—
2.5
—
—
4
—
—
6
—
1.5
—
1.5
1.5
—
1.5
0.6
0.4
0.6
= AV
= 0 V, ø = 2 MHz to 8
SS
SS
= –40°C to +85°C (wide-
a
= AV
= 0 V, ø = 2 MHz to 10
SS
SS
= –40°C to +85°C (wide-
a
= AV
= 0 V, ø = 2 MHz to 18
SS
= –40°C to +85°C (wide-
a
Condition C
18 MHz
Min
Max
Unit
—
100
ns
50
—
50
—
1.5
—
t
cyc
2.5
—
4
—
6
—
—
1.5
—
1.5
0.4
0.6
t
Scyc
Test
Conditions
Figure 18-15
Figure 18-16
Figure 18-17
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