Hitachi F-ZTAT H8/3039 Series Hardware Manual page 304

Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered
by different compare match events, the address of the upper 4 bits of NDRB (group 3)* is H'FFA4
and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7
to 4 of address H'FFA6 are reserved bits that cannot be modified and always read 1.
Note: * Since this LSI does not have a TP
Address H'FFA4
Bit
NDR15
Initial value
Read/Write R/W
Address H'FFA6
Bit
Initial value
Read/Write
294
7 6
NDR14 NDR13
0 0
R/W R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
7 6
— —
1 1
— —
Reserved bits
pin, the TP signal cannot be output off-chip.
14 14
5 4
NDR12
0 0
R/W
5 4
— — NDR11
1 1
— — R/W
3 2
— —
1 1
— —
Reserved bits
3 2
NDR10 NDR9
0 0
R/W R/W
Next data 11 to 8
These bits store the next output
data for TPC output group 2
1 0
— —
1 1
— —
1 0
NDR8
0 0
R/W