Hitachi F-ZTAT H8/3039 Series Hardware Manual page 294

Table 8-11 (e) ITU Operating Modes (Channel 4)
TSNC
Synchro-
Operating Mode nization MDF
Synchronous preset SYNC4 = 1 —
PWM mode —
Output compare A —
Output compare B —
Input capture A —
Input capture B —
Counter By compare —
clearing match/input
capture A
By compare —
match/input
capture B
Syn- SYNC4 = 1 —
chronous
clear
Complementary —
*3
PWM mode
Reset-synchronized —
PWM mode
Buffering —
(BRA)
Buffering —
(BRB)
Legend: Setting available (valid). — Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. When reset-synchronized PWM mode is selected, TCNT4 operates independently and the counter clearing function is available. Waveform output is not affected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. TCR4 settings are valid in reset-synchronized PWM mode, but TCNT4 operates independently, without affecting waveform output.
TMDR TFCR
Comple- Reset-
mentary Synchro-
FDIR PWM PWM nized PWM Buffering
— * 3
— PWM4 = 1 CMD1 = 0 CMD1 = 0
— PWM4 = 0 CMD1 = 0 CMD1 = 0
— CMD1 = 0 CMD1 = 0
— PWM4 = 0 CMD1 = 0 CMD1 = 0
— PWM4 = 0 CMD1 = 0 CMD1 = 0
— Illegal setting:
*4
CMD1 = 1
CMD0 = 0
— Illegal setting:
*4
CMD1 = 1
CMD0 = 0
— Illegal setting:
*4
CMD1 = 1
CMD0 = 0
— — CMD1 = 1 CMD1 = 1
CMD0 = 0 CMD0 = 0
— — CMD1 = 1 CMD1 = 1
CMD0 = 1 CMD0 = 1
—
—
Register Settings
TOCR TOER
Output
Level Master
XTGD Select Enable
— — *1
— —
— —
— —
— — EA4 ignored IOA2 = 1
Other bits
unrestricted unrestricted
— — EB4 ignored
Other bits
unrestricted
— —
* 1
— —
*1
— — * 1
BFA4 = 1 — —
*1
Other bits
unrestricted
BFB4 = 1 — — *1
Other bits
unrestricted
TIOR4 TCR4
Clear Clock
IOA IOB Select Select
— *2
IOA2 = 0
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
Other bits
IOB2 = 1
Other bits
unrestricted
CCLR1 = 0
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 1
CCLR0 = 1
— — CCLR1 = 0
CCLR0 = 0
— — *6
*5
*6