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7.10.2 Register Descriptions
Table 7-15 summarizes the registers of port A.
Table 7-15 Port A Registers
Address*
Name
H'FFD1
Port A data direction
register
H'FFD3
Port A data register
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. The corresponding PADDR bit should also be set when a
pin is used as a TPC output.
Bit
Modes
Initial value
1, 5, and 7
Read/Write
Initial value
Mode 3
Read/Write
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. However, in mode 3, PA
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 in modes 1, 5 and 7 and to H'80 in mode 3 by a reset and in
hardware standby mode. In software standby mode it retains its previous setting. If a PADDR bit
is set to 1, the corresponding pin maintains its output state in software standby mode.
Abbreviation
PADDR
PADR
7
6
PA DDR
PA DDR
PA DDR
7
6
0
0
W
W
1
0
—
W
Initial Value
R/W
Modes 1, 5, and 7
W
H'00
R/W
H'00
5
4
3
PA DDR
PA DDR
5
4
3
0
0
0
W
W
W
0
0
0
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
DDR is fixed at 1, and PA7 functions as an
7
Mode 3
H'80
H'00
2
1
PA DDR
PA DDR
PA DDR
2
1
0
0
W
W
0
0
W
W
0
0
0
W
0
W
167
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