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Table 1-1 Features
Feature
CPU
Memory
Interrupt
controller
Bus controller
2
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
•
Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
•
Maximum clock rate: 18 MHz
•
Add/subtract: 111 ns
•
Multiply/divide: 778 ns
Two CPU operating modes
•
Normal mode (64-kbyte address space)
•
Advanced mode (16-Mbyte address space)
Instruction features
•
8/16/32-bit data transfer, arithmetic, and logic instructions
•
Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
•
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
•
Bit accumulator function
•
Bit manipulation instructions with register-indirect specification of bit positions
H8/3039
•
ROM: 128 kbytes
•
RAM: 4 kbytes
H8/3038
•
ROM: 64 kbytes
•
RAM: 2 kbytes
H8/3037
•
ROM: 32 kbytes
•
RAM: 1 kbyte
H8/3036
•
ROM: 16 kbytes
•
RAM: 512 bytes
•
Five external interrupt pins: NMI, IRQ
•
25 internal interrupts
•
Three selectable interrupt priority levels
•
Address space can be partitioned into eight areas, with independent bus
specifications in each area
•
Two-state or three-state access selectable for each area
•
Selection of four wait modes
, IRQ
, IRQ
, IRQ
0
1
4
5
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