Hitachi F-ZTAT H8/3039 Series Hardware Manual page 218

Bit 1—Master Enable TIOCA
Bit 1
EA4 Description
0 TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA
4
operates as a generic input/output pin).
If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.
1 TIOCA is enabled for output according to TIOR4, TMDR, and TFCR
4
settings
Bit 0—Master Enable TIOCA
Bit 0
EA3 Description
0 TIOCA output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA
3
operates as a generic input/output pin).
If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.
1 TIOCA is enabled for output according to TIOR3, TMDR, and TFCR
3
settings
208
(EA4): Enables or disables ITU output at pin TIOCA
4
(EA3): Enables or disables ITU output at pin TIOCA
3
.
4
4
(Initial value)
.
3
3
(Initial value)