Hitachi F-ZTAT H8/3039 Series Hardware Manual page 473

Increment
verify address
No
Notes: 1. Preprogramming (setting erase block data to all 0s) is not necessary.
2. The values of x, y, z, α, β, γ, ε, η, and N are shown in section 18.2.5, Flash Memory Characteristics.
3. Verify data is read in 16-bit (word) units. (Byte-unit reading is also possible.)
4. Set only one bit in EBR two or more bits must not be set simultaneously.
5. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Figure 15-12 Erase/Erase-Verify Flowchart (Single-Block Erasing)
464
*1
Start
Set SWE bit in FLMCR
Wait (x) µsec
Erase counter n ← 1
Set EBR
Enable WDT
Set ESU bit in FLMCR
Wait (y) µsec
Set E bit in FLMCR
Wait (z) msec
Clear E bit in FLMCR
Wait (α) µsec
Clear ESU bit in FLMCR
Wait (β) µsec
Disable WDT
Set EV bit in FLMCR
Wait (γ) µsec
Set block start address
to verify address
H'FF dummy write to verify address
Wait (ε) µsec
Read verify data
Verify data = H'FFFF?
YES
Last address of block?
Yes
Clear EV bit in FLMCR
Wait (η) µsec
Clear SWE bit in FLMCR
End of erasing
*2
*4
*5
*2
Start of erase
*2
End of erase
*2
*2
*2
*2
*3
No
n ← n + 1
*2
Clear EV bit in FLMCR
Wait (η) µsec
n>N?
Clear SWE bit in FLMCR
Erase failure
Re-erase
*2
*2
No
Yes