Output Timing - Hitachi F-ZTAT H8/3039 Series Hardware Manual

Single-chip microcomputer
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9.3.2 Output Timing

If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 9-3 shows the timing of these operations
for the case of normal output in groups 0 and 1, triggered by compare match A.
ø
TCNT
GRA
Compare
match A signal
NDRA
PADR
TP to TP
0
7
Figure 9-3 Timing of Transfer of Next Data Register Contents and Output (Example)
N
N + 1
N
n
m
m
n
n
303

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