Hitachi F-ZTAT H8/3039 Series Hardware Manual page 684

Reset in T3 State: Figure D-3 is a timing diagram for the case in which RES goes low during the
state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
T
3
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus outputs are held during the T
T state of an access cycle to a two-state-access area.
2
ø
RES
Internal
reset signal
Address bus
(modes 1, 3, 5)
AS (modes 1, 3, 5)
RD (read access)
(modes 1, 3, 5)
WR (write access)
(modes 1, 3, 5)
Data bus
(write access)
(modes 1, 3, 5)
I/O port
(modes 1, 3, 5 to 7)
Figure D-3 Reset during Memory Access (Reset during T3 State)
678
state.The same timing applies when a reset occurs in the
3
Access to external address
T T
1 2
T
3
H'000000
High impedance
High impedance