Division Control Register (Divcr); Usage Notes - Hitachi F-ZTAT H8/3039 Series Hardware Manual

16.5.2 Division Control Register (DIVCR)

DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
Initial value
Read/Write
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as
follows.
Bit 1 Bit 0
DIV1 DIV0
0 0
0 1
1 0
1 1

16.5.3 Usage Notes

The DIVCR setting changes the ø frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time t
settings that give system clock frequencies less than 1 MHz.
All on-chip module operations are based on ø. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in the
division ratio. The waiting time for exit from software standby mode also changes when the
division ratio is changed. For details, see section 17.4.3, Selection of Oscillator Waiting Time
After Exit from Software Standby Mode
7 6
— —
1 1
— —
Reserved bits
Frequency Division Ratio
1/1
1/2
1/4
1/8
in the AC electrical characteristics. Note that ø
cyc
5 4
— —
1 1
— —
3 2
— — DIV1
1 1
— — R/W
Divide bits 1 and 0
These bits select the
frequency division ratio
= 1 MHz. Avoid
MIN
1 0
DIV0
0 0
R/W
(Initial value)
499