Hitachi F-ZTAT H8/3039 Series Hardware Manual page 207

Table 8-3 ITU Registers (cont)
Channel Address*
4 H'FF92
H'FF93
H'FF94
H'FF95
H'FF96
H'FF97
H'FF98
H'FF99
H'FF9A
H'FF9B
H'FF9C
H'FF9D
H'FF9E
H'FF9F
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
1
Name
Timer control register 4
Timer I/O control register 4
Timer interrupt enable register 4
Timer status register 4
Timer counter 4 (high)
Timer counter 4 (low)
General register A4 (high)
General register A4 (low)
General register B4 (high)
General register B4 (low)
Buffer register A4 (high)
Buffer register A4 (low)
Buffer register B4 (high)
Buffer register B4 (low)
Abbre-
viation R/W
TCR4 R/W
TIOR4 R/W
TIER4 R/W
2
TSR4 R/(W)*
TCNT4H R/W
TCNT4L R/W
GRA4H R/W
GRA4L R/W
GRB4H R/W
GRB4L R/W
BRA4H R/W
BRA4L R/W
BRB4H R/W
BRB4L R/W
Initial
Value
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
197