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D.1 Port States in Each Mode
Table D-1 Port States
Pin Name
Mode
ø
—
RESO*
1
—
P1
to P1
1, 3
7
0
5
6, 7
P2
to P2
1, 3
7
0
5
6, 7
P3
to P3
1, 3, 5
7
0
6, 7
P5
to P5
1, 3
3
0
5
6, 7
P6
1, 3, 5
0
6, 7
P6
to P6
1, 3, 5
5
3
6, 7
Legend
H:
High
L:
Low
T:
High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
674
Appendix D Pin States
Hardware
Standby
Reset State
Mode
Clock output T
2
T*
T
L
T
T
T
T
T
L
T
T
T
T
T
T
T
T
T
L
T
T
T
T
T
T
T
T
T
H
T
T
T
Software
Program
Standby
Execution State
Mode
Sleep Mode
H
Clock output
RESO
T
T
A
to A
7
keep
Input port (DDR = 0)
T
A
to A
7
keep
I/O port
T
A
to A
15
keep
Input port (DDR = 0)
T
A
to A
15
keep
I/O port
T
D
to D
7
keep
I/O port
T
A
to A
19
keep
Input port (DDR = 0)
T
A
to A
19
keep
I/O port
I/O port, WAIT
keep
keep
I/O port
WR, RD, AS
T
keep
I/O port
0
(DDR = 1)
0
8
(DDR = 1)
8
0
16
(DDR = 1)
16
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