Hitachi F-ZTAT H8/3039 Series Hardware Manual page 5

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) .............................................
5.2.3 IRQ Status Register (ISR) .................................................................................... 91
5.2.4 IRQ Enable Register (IER) .................................................................................. 92
5.2.5 IRQ Sense Control Register (ISCR).....................................................................
5.3 Interrupt Sources................................................................................................................ 94
5.3.1 External Interrupts................................................................................................ 94
5.3.2 Internal Interrupts ................................................................................................. 95
5.3.3 Interrupt Vector Table .......................................................................................... 95
5.4 Interrupt Operation ............................................................................................................ 98
5.4.1 Interrupt Handling Process ...................................................................................
5.4.2 Interrupt Sequence................................................................................................ 103
5.4.3 Interrupt Response Time ...................................................................................... 104
5.5 Usage Notes ....................................................................................................................... 105
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 105
5.5.2 Instructions that Inhibit Interrupts........................................................................ 106
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 106
5.5.4 Usage Notes.......................................................................................................... 106
Section 6 Bus Controller
6.1 Overview............................................................................................................................ 109
6.1.1 Features ................................................................................................................ 109
6.1.2 Block Diagram...................................................................................................... 110
6.1.3 Input/Output Pins.................................................................................................. 111
6.1.4 Register Configuration ......................................................................................... 111
6.2 Register Descriptions......................................................................................................... 112
6.2.1 Access State Control Register (ASTCR).............................................................. 112
6.2.2 Wait Control Register (WCR).............................................................................. 113
6.2.3 Wait State Controller Enable Register (WCER) .................................................. 114
6.2.4 Address Control Register (ADRCR).................................................................... 115
6.3 Operation ........................................................................................................................... 117
6.3.1 Area Division........................................................................................................ 117
6.3.2 Bus Control Signal Timing .................................................................................. 119
6.3.3 Wait Modes .......................................................................................................... 121
6.3.4 Interconnections with Memory (Example) .......................................................... 127
6.4 Usage Notes ....................................................................................................................... 129
6.4.1 Register Write Timing.......................................................................................... 129
6.4.2 Precautions on setting ASTCR and ABWCR* .................................................... 129
Section 7 I/O Ports
7.1 Overview............................................................................................................................ 131
7.2 Port 1.................................................................................................................................. 135
7.2.1 Overview .............................................................................................................. 135
7.2.2 Register Descriptions............................................................................................ 135
................................................................................................ 109
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